1. Field of the Invention
The present invention relates to the field of semiconductor integrated circuit manufacturing, and more specifically, to a method of optimizing a sample plan for measuring overlay.
2. Discussion of Related Art
Integrated Circuit (IC) devices may be fabricated on a substrate, such as a wafer, that is usually made from semiconducting material, such as silicon. Various types of materials may be added to, or removed from, the wafer during processing. The materials may include insulating material, such as silicon oxide, or conducting material, such as copper.
Some processes that may be used to add a material to the wafer include chemical vapor deposition, sputtering, electroplating, oxidation, and ion implantation. Other processes that may be used to remove a material, partially or completely, from the wafer include wet etching, dry etching, and chemical-mechanical polishing. Photolithography may be used to selectively process certain portions of the wafer.
Many parameters of the IC devices must be monitored during fabrication to ensure that the specifications for performance and reliability may be met. Since IC device fabrication involves many layers, it is important to ensure that the overlay, or placement of a layer relative to another layer, falls within a certain acceptable tolerance.
However, as the wafer becomes larger and the design rules become tighter, a sample plan for measuring overlay may be difficult to optimize.